koppar.ai

How to drive Koppar end to end, and the instructions for each stage you do yourself: "research" (part research and the dossier), "synthesis" (writing the SKiDL schematic), "review" (design review), "board" (the board plan).

Start a new design from the user's brief (what the board must do, its interfaces, power, size and constraints).

The user's designs, newest first, including ones made in the web app (an agent can continue those too).

Where a design stands: the brief, the schematic (accepted or the last blocking error, ERC, part and net counts, submissions), the board run, the readable files, and the next step.

Search KiCad's standard symbol libraries for parts whose name contains a substring.

Return the full pin list (number, name, electrical type) and description for a specific KiCad symbol.

Search KiCad's standard footprint libraries.

Register a connectable schematic symbol for a part that is NOT in KiCad's libraries (search_kicad_symbol returned nothing).

Store the research dossier (markdown with ## Parts list, ## Power rails, ## Topology constraints, ## Notes, as the research guide describes).

Compile and check a complete SKiDL script: the symbol and footprint pre-flight (unambiguous typos are corrected and listed), SKiDL, the ERC score, KiCad ERC, floating subsystems, parts without a footprint, and supplier sourcing.

Apply SEARCH/REPLACE patches to your latest script and re-run every check, as submit_circuit does.

Read a text file of the design: prompt.

Everything a design review needs in one text: the brief, the dossier, circuit.

What the board plan is decided from: the computed minimum board, BOARD STATS (pad density, fine-pitch parts, fanout), the parts and nets, board instructions the user gave, and the plan schema with its rules.

Start place and route with your board plan (the JSON object from the board guide: board, stated, edge, chain, groups, near, side, fixed, keepouts, netClasses).

The board run: stage, size, layers, placement, routing completion, open nets, DRC counts; once finished, DRC violations by type, whether the fab files are released and, when not, the diagnosed causes (first = fix first: parts that did not fit, collisions, missing footprints, open nets, thin power).

The live-priced BOM: each line with references, value, footprint, the chosen offer (seller, part number, MPN, price, stock, match quality), alternatives and totals.

Pick which offer a BOM line uses: the line's references and a seller part number or MPN from its offer or alternatives in get_bom; null goes back to the automatic pick.

Whether the board has earned its fab files (zero serious DRC errors, nothing unconnected), and if not, why not.

The PCB and assembly providers, whether each can quote and take this kind of board today, and what a handoff sends them.

One price for a quantity: parts from the sellers, the board and assembly from the chosen provider's quote, setup fees, and what the total does not include.

Upload the released board (Gerbers, BOM, placement) to a manufacturer and return the page where the user pays.

Replace the design's board with a .

Download URLs for the design (KiCad project, schematic, netlist, BOM CSV, board file, 3D model, Gerbers, order bundle) and which are available now.

Bring an existing KiCad project in as a board workspace: the project folder as a ZIP (the .

The board as it stands: copper layers, outline, design rules and net classes, counts (footprints, nets, tracks, vias, zones, keepouts, KiCad unconnected items), zones and keepouts, and every footprint with reference, value, footprint, position (origin, mm), rotation, side, locked, DNP, courtyard box and 3D models.

Put footprints exactly where given: KiCad board coordinates of the footprint origin in mm (y grows downward), rotation in degrees as KiCad shows it, side F or B (changing side flips the footprint, as KiCad does), locked.

Pack footprints inside the board outline with Koppar's heuristic placer (ratsnest-driven, courtyard-legal).

Dense placement by simulated annealing: wirelength inside the outline with courtyard gaps, edge connectors held on their edge, fixed and locked parts held, keepout rectangles kept clear (routing corridors), and a per-pad price for the bottom side (flip_cost, mm of wirelength; each bottom-side pad whose net has top-side pins costs a via).

Replace everything on Edge.

Set the project design rules (.

Add or remove keepout rule areas.

Check the copper against the project's net classes and differential pairs, which KiCad's DRC does not: every class or pair net's narrowest track and the length below its class width, and every pair (X_P/X_N, X+/X-, CAN X_H/X_L) with its coupled share at the class's diff_pair_gap, both lengths and the skew.

Judge the copper by physics, which KiCad's DRC does not: impedance from the stackup on controlled nets, IR drop and heating on rails with a stated current, pair and lane skew, a ground via beside every high-speed layer change, 3W spacing between high-speed runs, and the via path under exposed paddles.

Add or remove copper zones (pours).

Lay exact copper by hand where the routers leave a gap: tracks as polylines on one copper layer, and through vias.

Remove every via the board does not need: groups of vias come out, the zones are refilled and KiCad's unconnected count compared, and a via stays only if removing it disconnects something.

Take clutter off the silkscreen.

Route under the project's rules and net classes.

Keep the copper of every net it already connects and route the nets still open around it: route_board with preserve_existing.

Delete tracks and vias: of the given nets, on the given layers (vias are not layer-filtered), with an end inside region, or all.

Sweep the routing: zero-length and duplicate tracks, stub tracks (a free end, and everything the track touches stays joined without it), and vias that meet their net on fewer than two layers.

Unpack a ZIP into the project folder, keeping its paths: new footprints into a .

Replace footprints in place with another footprint from a library in the project's fp-lib-table (library:name): the reference, value, position, rotation (or rot_deg), side, lock and schematic link stay, and nets move pad by pad.

Refill every copper zone with KiCad's zone filler.

Tie neighbouring same-net SMD pads of the plane nets (GND, the rails with a pour) together on their own layer with short tracks, so a group shares one via to the plane instead of one via per pad, as a designer does.

Grow the tracks (and optionally vias) of the named nets in place, each as wide as its clearance to every other net's copper, holes and the board edge allows, up to the net's target width.

Close what the router left open the way a designer does: for each open net the diagnosis names the copper boxing it in; that copper is ripped (never a poured net), the open nets are routed FIRST into the space, then the ripped nets go back around them; up to `rounds` rounds, each kept only if KiCad counts fewer unconnected items.

A filled pour cut into islands by routing: one through-via per island that KiCad finds cut off from its net, placed well inside the island and inside the net's main copper on another layer, clear of every other net between.

After routing: every run redrawn as the fewest 0/45/90-degree segments that clear, and every track narrower than its net's netclass width widened where it fits (slid sideways, bumped around a lone obstacle, or necked only over the stretch that needs it; a via or thin track of another net moved aside when that is all that is in the way).

After route_board and prune_vias: rip one net at a time, most vias first, route it alone around everything else at a high via price, and keep the new copper only when KiCad counts fewer vias with no new open item or DRC error (a reroute that cuts a pour into islands first gets one via per island, bridge_islands).

After route_board: re-route the weakly coupled differential pairs one at a time, least coupled first.

For every net still open (or the nets named): each pad with the escape corridors free on its own layer, whether a via can be dropped beside it at all, and what blocks it (which part's pads, which net's tracks or vias, the board edge).

The numbers a designer judges routed copper by — signal vias per net, share of signal nets without a via, share of signal copper on the outer layers, vias in SMD pads, plane stitching — next to the bands of designer-routed reference boards with the same layer count, and a gap_to_designers list saying where this board is not yet human-grade.

KiCad's DRC on the board as it is now, with schematic parity when the project has its schematic: error and warning counts by type, shorts, unconnected items, parity items, and the first violations with their items and positions (types filters, max_violations caps; default 40).

Export the assembled board (3D models, DNP parts left out) and measure it: bounding-box size and volume, via count, copper layers, and the PCBGolf score = volume (mm³) + 50 × vias + 5000 × copper layers.

An exact 2D picture of the board as an engineer reads it: copper per layer (the facing layer full strength, the others faded), pads, vias, pours, outline, courtyards and refs.

Export the assembled board as STEP (3D models, DNP parts left out).

The snapshots of this board, newest first.

Put the board and its rules back as they were in a revision from list_board_revisions.

The design's latest board job: its status and, once it ends, its result or error.